AMD—Senior Functional Verification Engineer (Memory Subsystem)

Job description

Description: ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. MTS Engineer to provide technical leadership and contribution on high speed interface Verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block and Sun-System level, to prove the functional correctness of UCIe, DDR5/6 RLD3 Memory Controllee Designs. The ideal candidate is one who has a proven track record on driving strategies and successful verification execution high performance IPs and/or SOC designs. Require hands on experience with verification of state of the art memory controllers such as HBM, DDR, LPDDR, UCIe. Requires strong understanding of current memory controller protocols and calibration board skew and jitter modeling. With a proven track record in technical leadership of teams. This includes planning, execution, tracking, verification closure, and delivery to programs. Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality. Qualifications: - BS w/ 8+ yrs or MS w/ 7+ yrs or PhD w/ 7+ yrs in Electrical Engineering, Computer Engineering or Computer Science. - Experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory controller IPs. - Proven track record on driving strategies and successful verification execution on Memory Controllers high performance IPs and/or SOC designs. - Proven track record in technical leadership of teams of 9+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. - Hands on experience with verification of high speed interface like UCIe is a plus - Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus. - Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management. - Experience with formal property checking tools such as Cadence , Jasper and Synopsys is a plus. - Experience with gate level simulation, power verification, reset verification, contention checking is a plus. - Prior experience with silicon debug at the tester and board level, is a plus. #LI-NR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. Responsibilities: MTS Engineer to provide technical leadership and contribution on high speed interface Verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block and Sun-System level, to prove the functional correctness of UCIe, DDR5/6 RLD3 Memory Controllee Designs. The ideal candidate is one who has a proven track record on driving strategies and successful verification execution high performance IPs and/or SOC designs. Require hands on experience with verification of state of the art memory controllers such as HBM, DDR, LPDDR, UCIe. Requires strong understanding of current memory controller protocols and calibration board skew and jitter modeling. With a proven track record in technical leadership of teams. This includes planning, execution, tracking, verification closure, and delivery to programs. Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality. Qualifications: - BS w/ 8+ yrs or MS w/ 7+ yrs or PhD w/ 7+ yrs in Electrical Engineering, Computer Engineering or Computer Science. - Experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory controller IPs. - Proven track record on driving strategies and successful verification execution on Memory Controllers high performance IPs and/or SOC designs. - Proven track record in technical leadership of teams of 9+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. - Hands on experience with verification of high speed interface like UCIe is a plus - Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus. - Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management. - Experience with formal property checking tools such as Cadence , Jasper and Synopsys is a plus. - Experience with gate level simulation, power verification, reset verification, contention checking is a plus. - Prior experience with silicon debug at the tester and board level, is a plus. #LI-NR1