AMD—PD Leadership role

Job description

Description: ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: As a member of the S3 India physical design team, you will help bring to life cutting-edge designs. As a member and lead of the Physical design implementation team, you will work closely with the SOC architects, Fellows/Sr Fellows, Cross functional leads, Customers, Design leads, IP teams, Physical Design leads and PD/STA engineers to achieve first-pass silicon success. You will be expected to innovate and lead, design implementation and convergence activities in the RTL2GDSII SOC implementation perspective. In this position as a Physical Design Expert, you will be part of a world-class team developing groundbreaking high-performance SOCs/ASICS for DPU/APU/GPU/Others designs. These products are targeted for AI Data Centre, Game Consoles, High-end Discrete Graphics, Thin and Light Laptops, Artificial Intelligence solutions for Inference/Training, Telecommunication, Automotive applications and more. This is a great opportunity to join a talented team that is well-invested in the implementation of futuristic designs in advanced process nodes. THE PERSON: As a PD (Physical Design) Architect, we are seeking a highly experienced and innovative person, who will be responsible for driving Physical Design, Timing closure, Power Optimization and Signoff strategies, methodologies, setting industry standards flows along with spearheading multiple SOC/ASICs execution for the successful delivery of project tape-outs from RTL2GDSII. You will use your knowledge of Physical design and timing closure to lead a complete set of activities, specifically Synthesis, Constraints, PnR, Timing, Physical Verification and Signoff, including IP integration and full-chip signoff aspects. Your leadership and strategic vision will guide the development of methodologies that optimize SOC development cycle. Additionally, you will mentor team members and effectively communicate complex technical concepts to align stakeholders and drive successful implementation. This position requires a detail-oriented candidate who possesses good communication skills and can handle/work with teams. KEY RESPONSIBILITIES: - Go to person for multiple SOC/ASICs in RTL2GDSII domain comprising of physical design implementation, timing closure and various signoff (timing, physical verification, IREM, Power etc) activities - Provide leadership and mentoring towards convergence of highly complex tiles/partitions/blocks spanning across multiple Subsystems and IPs , not limited to PCIE, DDR, CPUs, GPUs, Gfx, ETH, UCIE etc. - Cross-Functional Leadership - Collaborate with various teams, including architecture, design, verification, DFT and product management, to ensure PPA goals are met. - Strategic Planning: Provide strategic direction to SOC/Subsystem and Tile/Partition level execution, that align with industry trends and company goals. - Foster a culture of innovation by encouraging research and experimentation in RTL2GDSII activities. Identify opportunities for patents and publications. - Good understanding of horizontal sign-off flows like VCLP, Formal Equivalence, Low Power Checks with expert level understanding of timing convergence (both tile-level and full chip timing), and full chip integration flows. - Understanding of design requirements, timelines and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle. - Drive methodology development ideas and drive internal forums towards adoption of latest flow/methodologies and AI technologies. - Collaborate with CAD and EDA vendors to further strengthen AMD and S3 PD closure methodology. - Provide technical direction, guidance, mentorship and support to the engineering team. - Stay abreast of the latest advancements in RTL2GDSII and represent the company in industry forums, conferences, and collaborations to influence and adopt best practices. - Define and track key performance indicators (KPIs) related RTL2GDSII . Report on progress and impact to senior leadership and executives. - Possess good understanding of foundry DRM and must have collaborated with DTCO and FTO in the past PREFERRED EXPERIENCE: - Experienced PD/Timing professional with a minimum of 15 years of industry experience in the Physical design domain (RTL to GDS, STA, Physical verification, timing signoff, tapeout). - SOC and Block-level implementation (Place and Route), which includes Floorplanning, Timing Closure and Physical Verification. - Well-versed with Physical Design verification signoff techniques such as Formal Equivalence, IR&EM, Timing Closure (STA), Physical verification, VSI, Formal Equivalence Check or LEC, etc. - Expert level understanding of Power, Performance and Area (PPA) optimisation techniques. - Hands on experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design and latest use of AI technologies - Expert level understanding of EDA tools across Synopsys and Cadence - Excellent presentation and inter-communication skills. Qualifications: - B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering. - Candidate must have the ability to drive/manage projects from RTL to GDS, with a minimum experience of managing more than 5-10 tape-outs. - Proficient in physical design industry-standard EDA tools like Fusion compiler/ICC2/Primetime/Redhawk/PTPX, low power and physical verification tools. - #LI-BM2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. Responsibilities: THE ROLE: As a member of the S3 India physical design team, you will help bring to life cutting-edge designs. As a member and lead of the Physical design implementation team, you will work closely with the SOC architects, Fellows/Sr Fellows, Cross functional leads, Customers, Design leads, IP teams, Physical Design leads and PD/STA engineers to achieve first-pass silicon success. You will be expected to innovate and lead, design implementation and convergence activities in the RTL2GDSII SOC implementation perspective. In this position as a Physical Design Expert, you will be part of a world-class team developing groundbreaking high-performance SOCs/ASICS for DPU/APU/GPU/Others designs. These products are targeted for AI Data Centre, Game Consoles, High-end Discrete Graphics, Thin and Light Laptops, Artificial Intelligence solutions for Inference/Training, Telecommunication, Automotive applications and more. This is a great opportunity to join a talented team that is well-invested in the implementation of futuristic designs in advanced process nodes. THE PERSON: As a PD (Physical Design) Architect, we are seeking a highly experienced and innovative person, who will be responsible for driving Physical Design, Timing closure, Power Optimization and Signoff strategies, methodologies, setting industry standards flows along with spearheading multiple SOC/ASICs execution for the successful delivery of project tape-outs from RTL2GDSII. You will use your knowledge of Physical design and timing closure to lead a complete set of activities, specifically Synthesis, Constraints, PnR, Timing, Physical Verification and Signoff, including IP integration and full-chip signoff aspects. Your leadership and strategic vision will guide the development of methodologies that optimize SOC development cycle. Additionally, you will mentor team members and effectively communicate complex technical concepts to align stakeholders and drive successful implementation. This position requires a detail-oriented candidate who possesses good communication skills and can handle/work with teams. KEY RESPONSIBILITIES: - Go to person for multiple SOC/ASICs in RTL2GDSII domain comprising of physical design implementation, timing closure and various signoff (timing, physical verification, IREM, Power etc) activities - Provide leadership and mentoring towards convergence of highly complex tiles/partitions/blocks spanning across multiple Subsystems and IPs , not limited to PCIE, DDR, CPUs, GPUs, Gfx, ETH, UCIE etc. - Cross-Functional Leadership - Collaborate with various teams, including architecture, design, verification, DFT and product management, to ensure PPA goals are met. - Strategic Planning: Provide strategic direction to SOC/Subsystem and Tile/Partition level execution, that align with industry trends and company goals. - Foster a culture of innovation by encouraging research and experimentation in RTL2GDSII activities. Identify opportunities for patents and publications. - Good understanding of horizontal sign-off flows like VCLP, Formal Equivalence, Low Power Checks with expert level understanding of timing convergence (both tile-level and full chip timing), and full chip integration flows. - Understanding of design requirements, timelines and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle. - Drive methodology development ideas and drive internal forums towards adoption of latest flow/methodologies and AI technologies. - Collaborate with CAD and EDA vendors to further strengthen AMD and S3 PD closure methodology. - Provide technical direction, guidance, mentorship and support to the engineering team. - Stay abreast of the latest advancements in RTL2GDSII and represent the company in industry forums, conferences, and collaborations to influence and adopt best practices. - Define and track key performance indicators (KPIs) related RTL2GDSII . Report on progress and impact to senior leadership and executives. - Possess good understanding of foundry DRM and must have collaborated with DTCO and FTO in the past PREFERRED EXPERIENCE: - Experienced PD/Timing professional with a minimum of 15 years of industry experience in the Physical design domain (RTL to GDS, STA, Physical verification, timing signoff, tapeout). - SOC and Block-level implementation (Place and Route), which includes Floorplanning, Timing Closure and Physical Verification. - Well-versed with Physical Design verification signoff techniques such as Formal Equivalence, IR&EM, Timing Closure (STA), Physical verification, VSI, Formal Equivalence Check or LEC, etc. - Expert level understanding of Power, Performance and Area (PPA) optimisation techniques. - Hands on experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design and latest use of AI technologies - Expert level understanding of EDA tools across Synopsys and Cadence - Excellent presentation and inter-communication skills. Qualifications: - B.Tech/M.Tech/MS/Ph.D. in Computer/Electronics/Electrical Engineering. - Candidate must have the ability to drive/manage projects from RTL to GDS, with a minimum experience of managing more than 5-10 tape-outs. - Proficient in physical design industry-standard EDA tools like Fusion compiler/ICC2/Primetime/Redhawk/PTPX, low power and physical verification tools. - #LI-BM2