Texas Instruments—Layout Engineer

Job description

Description: Change the world. Love your job. Texas Instruments is seeking a Layout Engineer. In this role, you will develop and prepare multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. You may also check dimensions, write specifications, and verify completed drawings, artwork or digitized plots. Additional job functions may involve checking design layouts and detailed drawings, referring to offline layout leveling charts for details on duties. A bachelor's degree in engineering is typically required, and in the U.S. this job is restricted to specific job grades. Requirements: Minimum requirements: - Minimum education (ie bachelor's degree in electrical and electronics engineering) - Minimum of 2-5 years of experience Roles and responsibilities: - Frame the layout schedule, effort estimation, risk and mitigation plan of layout activities for all layout engineers in the project - Work closely with designers to understand the architecture and key requirements for the IC - Strike right balance of area, performance and schedule during layout development by collaborating with design, packaging and process teams - Work closely with Process development team to carry out PDK, P-cell and Design rule updates - Work closely with Packaging engineer to develop custom lead-frames for various packages - Analysis and closure of Electro Migration, Thermal gradients, ESD/LU performance and layout parasitic - Routinely develop test vehicles for new process & package technology development - Mentor and guide junior layout engineers/contract engineers, review their work and provide feedback to meet the quality and schedule norms - Responsible for the final layout which meets the design expectations and layout checklist. - Identify improvements needed in process/ quality/ cycle time and take up necessary initiatives Knowledge and skills: - Full chip layout experience from definition through release of IC to production - Strong LVS, DRC, ERC, and antenna debug skills - Proficient in analog and mixed-signal layout techniques and verification process including Device Matching, Power Bus design, avoiding Cross-talk, ESD/LU protection techniques - Good understanding about all layout parasitics (R, C, diodes, BJTs) - Good understanding of device physics and semiconductor fabrication process - Must have worked on some of the Technologies like: 40nm, 65nm, 90nm, 130nm, 180nm, BiCMOS - Should be well versed with tools such as Virtuoso XL/Assura /PVS/Voltas - Ability to quickly ramp up on new tools/ process and mentor LEs - Experience in automation/ SKILL coding for reducing cycle time/ quality checks will be an added advantage - Requires excellent teamwork, good communication, strong problem-solving and documentation skills. - Strong time management skills for on-time project delivery - Ability to take initiatives and drive for results