AMD—IP/Subsystem Verification Lead

Job description

Description: WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. PMTS SILICON DESIGN ENGINEER THE ROLE: AMD is looking for a talented individual to join the Network Technology Solutions Group in the Data Center Solutions Group as Principal Design Verification Engineer. This group designs and develops RTL blocks, subsystems, and SOCs for the AMD NTSG BU with product lines including AI NICs, low latency, High speed NIC, Networking of GPU clusters to be built to support AI training and inference workloads at scale. THE PERSON: As a Principal Design Verification Engineer, you will lead the verification efforts to functionally verify complex RTL blocks and SOCs destined for the next generation of Data Center networking ASICs KEY RESPONSIBILITIES: - Experience of working as a technical lead in a verification team - Proven track record in simulation-based verification for ASIC or FPGA blocks and subsystems. - Strong experience in UVM-based verification in SystemVerilog, with a deep understanding of the framework. - Experience of verification coverage closure in an ASIC or FPGA project. - Strong problem-solving skills. - Experience of Synopsys functional verification tools would be an advantage. - Experience of full chip verification would be an advantage. - Experience of formal verification would be an advantage. - Knowledge of AI-based debug techniques would be an advantage. - Knowledge of Python would be an advantage. - Experience in C/C++ would be an advantage. - RTL design experience would be an advantage. - Experience in networking technologies and products would be an advantage. PREFERRED EXPERIENCE: - Minimum 15 Year of experience in verification of VLSI systems ACADEMIC CREDENTIALS: - Bachelor’s or Master’s degree in related discipline preferred #LI-NS1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. Responsibilities: PMTS SILICON DESIGN ENGINEER THE ROLE: AMD is looking for a talented individual to join the Network Technology Solutions Group in the Data Center Solutions Group as Principal Design Verification Engineer. This group designs and develops RTL blocks, subsystems, and SOCs for the AMD NTSG BU with product lines including AI NICs, low latency, High speed NIC, Networking of GPU clusters to be built to support AI training and inference workloads at scale. THE PERSON: As a Principal Design Verification Engineer, you will lead the verification efforts to functionally verify complex RTL blocks and SOCs destined for the next generation of Data Center networking ASICs KEY RESPONSIBILITIES: - Experience of working as a technical lead in a verification team - Proven track record in simulation-based verification for ASIC or FPGA blocks and subsystems. - Strong experience in UVM-based verification in SystemVerilog, with a deep understanding of the framework. - Experience of verification coverage closure in an ASIC or FPGA project. - Strong problem-solving skills. - Experience of Synopsys functional verification tools would be an advantage. - Experience of full chip verification would be an advantage. - Experience of formal verification would be an advantage. - Knowledge of AI-based debug techniques would be an advantage. - Knowledge of Python would be an advantage. - Experience in C/C++ would be an advantage. - RTL design experience would be an advantage. - Experience in networking technologies and products would be an advantage. PREFERRED EXPERIENCE: - Minimum 15 Year of experience in verification of VLSI systems ACADEMIC CREDENTIALS: - Bachelor’s or Master’s degree in related discipline preferred #LI-NS1