Ericsson—Senior Engineer - Frontend CAD

Bangalore,Karnataka,India10+ yrs experienceTechPosted 28 Aug 2026Bachelor's (Engineering)

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Job description

<div><div style='padding: 10px 0px;border: 1px solid transparent;'><div style='font-size:16px;word-wrap: break-word;'><H2 style='font-size: 1em; margin: 0px'>Join our Team</H2></div><div><p><strong>About this opportunity:</strong></p><p>Are you a hands-on engineer and ready to shape the future of silicon verification methodology and tools on a global scale? </p><p>Join our Design Verification Methodology team — a newly established global group defining methodologies and EDA workflows across our R&D sites in Bangalore, Austin, Stockholm, and Lund. </p><p>We are part of the Ericsson Silicon engineering unit, developing state-of-the-art ASICs and FPGAs at advanced technology nodes for Ericsson’s 5G and 6G product portfolio. Our environment offers deep technical challenges, opportunities for growth, and a wealth of expertise to learn from. Last year we started a new Silicon R&D center in Bangalore, ready to join? </p></div></div><div style='padding: 10px 0px;border: 1px solid transparent;'><div style='font-size:16px;word-wrap: break-word;'><H2 style='font-size: 1em; margin: 0px'>You will do:</H2></div><div><div><ul><li><span xml:lang="EN-US" data-contrast="auto">In this high-visibility role, you will shape the next generation of </span><span xml:lang="EN-US" data-contrast="auto">Front-End CAD (FECAD)</span><span xml:lang="EN-US" data-contrast="auto"> methodologies, DV flows, and infrastructure for ASIC IP and SoC development.</span></li><li><span xml:lang="EN-US" data-contrast="auto">Major part of your work is to work with DV activities of our proprietary tools development. </span></li><li><span xml:lang="EN-US" data-contrast="auto">Your impact will be central in optimizing methodologies and EDA workflows, driving </span><span xml:lang="EN-US" data-contrast="auto">efficiency and innovation</span><span xml:lang="EN-US" data-contrast="auto"> across our global silicon engineering community.</span></li><li><span xml:lang="EN-US" data-contrast="auto">We are particularly interested in individuals with exposure to or interest in </span><span xml:lang="EN-US" data-contrast="auto">applying AI/ML techniques to silicon design and verification</span><span xml:lang="EN-US" data-contrast="auto"> — a significant plus as we invest in </span><span xml:lang="EN-US" data-contrast="auto">AI-driven design automation</span><span xml:lang="EN-US" data-contrast="auto">.</span></li><li><span xml:lang="EN-US" data-contrast="auto">If you thrive on solving technical challenges, spotting opportunities for improvement, and driving continuous innovation, we’d love to have you on our team.</span><span data-ccp-props="{"134233117":true,"134233118":true,"201341983":0,"335559740":240}"> </span></li></ul></div></div></div><div style='padding: 10px 0px;border: 1px solid transparent;'><div style='font-size:16px;word-wrap: break-word;'><H2 style='font-size: 1em; margin: 0px'>You will bring:</H2></div><div><ul><li><span xml:lang="EN-US" data-contrast="auto">Deep expertise in </span><span xml:lang="EN-US" data-contrast="auto">Testbench Architecture</span><span xml:lang="EN-US" data-contrast="auto"> using </span><span xml:lang="EN-US" data-contrast="auto">SystemVerilog and UVM</span><span xml:lang="EN-US" data-contrast="auto"> at IP, ASIC, and/or SoC level.</span></li><li><span xml:lang="EN-US" data-contrast="auto">Previous hands-on experience in scripting (Python, Perl, bash, csh, etc.).</span></li><li><span xml:lang="EN-US" data-contrast="auto">Strong knowledge of </span><span xml:lang="EN-US" data-contrast="auto">layered UVM environments</span><span xml:lang="EN-US" data-contrast="auto">, reusable testbench components, and block/subsystem/SoC-level verification strategies.</span></li><li><span xml:lang="EN-US" data-contrast="auto">Solid understanding of </span><span xml:lang="EN-US" data-contrast="auto">directed and constrained-random verification</span><span xml:lang="EN-US" data-contrast="auto">, SVA, functional and code coverage closure.</span></li><li><span xml:lang="EN-US" data-contrast="auto">Proficiency with front-end EDA tools: Verilog simulators, RTL/verification linters, CDC checkers, and formal verification.</span></li><li><span xml:lang="EN-US" data-contrast="auto">Experience with </span><span xml:lang="EN-US" data-contrast="auto">CI methodologies and tools</span><span xml:lang="EN-US" data-contrast="auto"> (e.g., Jenkins).</span></li><li><span xml:lang="EN-US" data-contrast="auto">Strong grasp of </span><span xml:lang="EN-US" data-contrast="auto">modern silicon design methodologies</span><span xml:lang="EN-US" data-contrast="auto"> and verification best practices.</span></li><li><span xml:lang="EN-US" data-contrast="auto">Experience collaborating across </span><span xml:lang="EN-US" data-contrast="auto">geographically distributed teams</span><span xml:lang="EN-US" data-contrast="auto">.</span></li><li><span xml:lang="EN-US" data-contrast="auto">Excellent communication skills and a strong sense of ownership in solving complex infrastructure challenges.</span></li><li><span xml:lang="EN-US" data-contrast="auto">Exposure to </span><span xml:lang="EN-US" data-contrast="auto">AI/ML applications in design and verification flows</span><span xml:lang="EN-US" data-contrast="auto"> (e.g., testbench optimization, anomaly detection, coverage prediction) is a </span><span xml:lang="EN-US" data-contrast="auto">significant advantage</span><span xml:lang="EN-US" data-contrast="auto">.</span><span data-ccp-props="{"134233117":true,"134233118":true,"201341983":0,"335559740":240}"> </span></li></ul></div></div><div style='padding: 10px 0px;border: 1px solid transparent;'><div style='font-size:16px;word-wrap: break-word;'><H2 style='font-size: 1em; margin: 0px'>Responsibilities:</H2></div><div><div><ul><li><span xml:lang="EN-US" data-contrast="auto">Lead</span><span xml:lang="EN-US" data-contrast="auto"> the development, verification, deployment, and support of complex front-end DV tools / flows.</span></li><li><span xml:lang="EN-US" data-contrast="auto">Identify and solve</span><span xml:lang="EN-US" data-contrast="auto"> flow, methodology, and tool inefficiencies across IP/ASIC/SoC environments; </span><span xml:lang="EN-US" data-contrast="auto">productize solutions</span><span xml:lang="EN-US" data-contrast="auto"> to improve silicon quality and verification productivity.</span></li><li><span xml:lang="EN-US" data-contrast="auto">Drive innovation</span><span xml:lang="EN-US" data-contrast="auto"> in design and verification processes, including AI-based enhancements.</span></li><li><span xml:lang="EN-US" data-contrast="auto">Collaborate closely with design, verification, test, and manufacturing teams to align on methodology, quality, and timelines.</span></li><li><span xml:lang="EN-US" data-contrast="auto">Troubleshoot</span><span xml:lang="EN-US" data-contrast="auto"> technical challenges and implement scalable, long-term solutions.</span></li><li><span xml:lang="EN-US" data-contrast="auto">Foster a </span><span xml:lang="EN-US" data-contrast="auto">collaborative, forward-looking culture</span><span xml:lang="EN-US" data-contrast="auto"> within the verification community.</span><span data-ccp-props="{"134233117":true,"134233118":true,"201341983":0,"335559740":240}"> </span></li></ul></div><div><p><span data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> </span></p></div><div><p><span xml:lang="EN-US" data-contrast="auto">Education & Experience</span><span data-ccp-props="{"134233117":true,"134233118":true,"201341983":0,"335559740":240}"> </span></p></div><div><ul><li><span xml:lang="EN-US" data-contrast="auto">BS/MS</span><span xml:lang="EN-US" data-contrast="auto"> in Electrical Engineering, Computer Science, or related field.</span></li><li><span xml:lang="EN-US" data-contrast="auto">10+ years</span><span xml:lang="EN-US" data-contrast="auto"> of relevant experience in ASIC design verification.</span><span data-ccp-props="{"134233117":true,"134233118":true,"201341983":0,"335559740":240}"> </span></li></ul></div></div></div><div style='padding: 10px 0px;border: 1px solid transparent;'><div style='font-size:16px;word-wrap: break-word;'><H2 style='font-size: 1em; margin: 0px'>*</H2></div><div><p><strong>“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”</strong></p></div></div></div><p><strong>Why join Ericsson?</strong>At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.<br> <br><strong>What happens once you apply?</strong><a title="http://www.ericsson.com/en/careers/hiring-process" href="http://www.ericsson.com/en/careers/hiring-process" target="_blank" rel="noreferrer noopener">Click Here</a> to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. <a title="http://www.ericsson.com/en/careers" href="http://www.ericsson.com/en/careers" target="_blank" rel="noreferrer noopener">learn more.</a></p><p> </p><p><strong>Primary country and city:</strong> India (IN) || Bangalore</p><p><strong>Req ID:</strong> 788102 </p>

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