AMD—DFx Verification

Job description

Description: ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SENIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: - Own DFx verification at block/IP, subsystem, and SoC level (scan/ATPG, LBIST/MBIST, JTAG/1149.x, boundary scan, test compression, repair, debug). - Develop and maintain SystemVerilog/UVM testbenches and tests for DFx, including stimulus, checkers, coverage, and scoreboards. - Define and execute DFx verification plans from specs/requirements; track and close using coverage‑driven metrics. - Build and maintain BFMs, agents, and monitors to verify interactions between DFx logic and key functional blocks (clocks, resets, power, fabric, memories). - Develop directed and constrained‑random tests for scan insertion, BIST, repair flows, test access, and debug/trace logic. - Run gate‑level simulations (including scan‑inserted netlists with SDF) to validate DFx behavior, test modes, and power‑up/reset sequences. - Partner with DFT/DFx architects and RTL designers to review micro‑architecture, catch corner cases, and drive DFx‑friendly designs. - Work with post‑silicon and product engineering to correlate pre‑silicon DFx results with silicon, support bring‑up, pattern debug, and yield/quality improvement. - Analyze coverage, identify gaps, and enhance test content and infrastructure to achieve DFx verification closure. - Maintain and improve DFx regression, debug, and automation flows (scripting, dashboards, CI). PREFERRED EXPERIENCE: - Strong experience in digital design verification using SystemVerilog and UVM (or similar modern verification methodologies). - Hands‑on experience with DFT/DFx concepts and flows such as:Scan, test compression, ATPG patterns - Logic BIST (LBIST) and Memory BIST (MBIST) - JTAG/IEEE 1149.x, boundary scan, and test access mechanisms - On‑chip debug, trace, and observability features - Understanding of SoC/CPU/GPU or complex ASIC design, including clocks, resets, CDC, and power intent (UPF/low‑power modes) as they relate to DFx. - Proficiency in C/C++ and/or SystemVerilog DPI for modeling, test content generation, or reference models. - Strong scripting skills in Python, Perl, Tcl, or Shell for automation, regressions, and data analysis. - Experience with hardware emulation or FPGA prototyping for DFx feature validation is a strong plus. - Familiarity with EDA tools and flows for simulation, coverage, lint, formal, ATPG/DFT, and gate‑level simulations. - Experience in silicon bring‑up, lab debug, or production test is a plus. Background in computing/graphics or high‑performance SoCs is an advantage. ACADEMIC CREDENTIALS: - Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. Responsibilities: SENIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: - Own DFx verification at block/IP, subsystem, and SoC level (scan/ATPG, LBIST/MBIST, JTAG/1149.x, boundary scan, test compression, repair, debug). - Develop and maintain SystemVerilog/UVM testbenches and tests for DFx, including stimulus, checkers, coverage, and scoreboards. - Define and execute DFx verification plans from specs/requirements; track and close using coverage‑driven metrics. - Build and maintain BFMs, agents, and monitors to verify interactions between DFx logic and key functional blocks (clocks, resets, power, fabric, memories). - Develop directed and constrained‑random tests for scan insertion, BIST, repair flows, test access, and debug/trace logic. - Run gate‑level simulations (including scan‑inserted netlists with SDF) to validate DFx behavior, test modes, and power‑up/reset sequences. - Partner with DFT/DFx architects and RTL designers to review micro‑architecture, catch corner cases, and drive DFx‑friendly designs. - Work with post‑silicon and product engineering to correlate pre‑silicon DFx results with silicon, support bring‑up, pattern debug, and yield/quality improvement. - Analyze coverage, identify gaps, and enhance test content and infrastructure to achieve DFx verification closure. - Maintain and improve DFx regression, debug, and automation flows (scripting, dashboards, CI). PREFERRED EXPERIENCE: - Strong experience in digital design verification using SystemVerilog and UVM (or similar modern verification methodologies). - Hands‑on experience with DFT/DFx concepts and flows such as:Scan, test compression, ATPG patterns - Logic BIST (LBIST) and Memory BIST (MBIST) - JTAG/IEEE 1149.x, boundary scan, and test access mechanisms - On‑chip debug, trace, and observability features - Understanding of SoC/CPU/GPU or complex ASIC design, including clocks, resets, CDC, and power intent (UPF/low‑power modes) as they relate to DFx. - Proficiency in C/C++ and/or SystemVerilog DPI for modeling, test content generation, or reference models. - Strong scripting skills in Python, Perl, Tcl, or Shell for automation, regressions, and data analysis. - Experience with hardware emulation or FPGA prototyping for DFx feature validation is a strong plus. - Familiarity with EDA tools and flows for simulation, coverage, lint, formal, ATPG/DFT, and gate‑level simulations. - Experience in silicon bring‑up, lab debug, or production test is a plus. Background in computing/graphics or high‑performance SoCs is an advantage. ACADEMIC CREDENTIALS: - Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-AA1