AMD—STA Silicon Design Engineer

Job description

Description: ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. MTS SILICON DESIGN ENGINEER  (STA/Timing) KEY RESPONSIBILITIES: - Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff - Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA - Well versed with timing signoff methodology and corner definitions - Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks - Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) - Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. - Ensuring full chip level Interface timing closure along DRV closure - Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure PREFERRED EXPERIENCE: - 8+ years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. - Experience with analyzing the timing reports and identifying both the design and constraints related issues. - Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc. - Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) - Strong Understanding of DFT modes requirements for timing signoff - Good understanding of physical design flow and ECO implementation. - Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. - Strong TCL/scripting knowledge is mandatory.   ACADEMIC CREDENTIALS:  - Bachelors or Masters degree in computer engineering/Electrical Engineering hip is an asset - Desirable assets with prior exposure to video codec system or other multimedia solutions.     ACADEMIC CREDENTIALS:  - Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-AB1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. Responsibilities: MTS SILICON DESIGN ENGINEER  (STA/Timing) KEY RESPONSIBILITIES: - Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff - Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA - Well versed with timing signoff methodology and corner definitions - Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks - Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) - Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. - Ensuring full chip level Interface timing closure along DRV closure - Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure PREFERRED EXPERIENCE: - 8+ years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. - Experience with analyzing the timing reports and identifying both the design and constraints related issues. - Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc. - Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) - Strong Understanding of DFT modes requirements for timing signoff - Good understanding of physical design flow and ECO implementation. - Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. - Strong TCL/scripting knowledge is mandatory.   ACADEMIC CREDENTIALS:  - Bachelors or Masters degree in computer engineering/Electrical Engineering hip is an asset - Desirable assets with prior exposure to video codec system or other multimedia solutions.     ACADEMIC CREDENTIALS:  - Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-AB1