AMD—SOC Verification with Post Silicon Validation

Job description

Description: ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. SOC Verification with Post Silicon Validation   THE ROLE: We are seeking a highly skilled and experienced SoC Verification Engineer with a proven track record in executing complex System-on-Chip (SoC) verification from planning to tape-out. In this role, you will lead and execute strategic verification for critical Server SoC infrastructures, specifically focusing on Advanced Power Management, Debug/Trace Architectures, and bridging the gap between Pre-Silicon Verification and Post-Silicon Validation. You will collaborate closely with Architecture, RTL Design, Firmware, and Lab Validation teams to ensure high-quality silicon execution   THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  - Power Management Verification: Architect and execute power-aware verification strategies. Validate low-power states, power controller units (PMU), dynamic voltage and frequency scaling (DVFS), and clock/reset sequencing using UPF/CPF-based simulations. - Debug Architecture Validation: Own the verification of complex SoC debug and trace infrastructure, including JTAG, hardware triggers, breakpoints, and specialized trace networks (e.g., ARM CoreSight). - C-Based & UVM Environments: Develop, scale, and maintain advanced hybrid verification environments leveraging both SystemVerilog/UVM and C/C++ direct environments for system-level use-case verification. - Post-Silicon Alignment: Author test content portable to emulation and post-silicon platforms. Collaborate with lab teams to mirror post-silicon failures in pre-silicon environments for rapid root-cause analysis. - Coverage & Sign-off: Drive complete functional, code, assertion (SVA), and scenario-based coverage closure to meet stringent silicon tape-out criteria   PREFERRED EXPERIENCE:  - - Core Experience: 8–12 years of hands-on experience in ASIC/SoC design verification with successful tape-out histories. - Low Power Expertise: Strong understanding of static and dynamic low-power concepts, UPF/CPF specifications, and Gate-Level Power-Aware Simulations (PAGLS). - Debug Protocol Knowledge: Deep understanding of JTAG, IEEE 1149.x, trace architectures, and processor-specific debug infrastructure (e.g., ARM, RISC-V, or x86). - Methodologies: Proficient in SystemVerilog, UVM, SystemVerilog Assertions (SVA), and assembly or C/C++ embedded programming for SoC bring-up. - SoC Infrastructure: Familiarity with high-speed protocols and fabrics, including AMBA (AXI, AHB, APB, CHI), memory controllers, and interrupt controllers.   ACADEMIC CREDENTIALS:  - Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. Responsibilities: SOC Verification with Post Silicon Validation   THE ROLE: We are seeking a highly skilled and experienced SoC Verification Engineer with a proven track record in executing complex System-on-Chip (SoC) verification from planning to tape-out. In this role, you will lead and execute strategic verification for critical Server SoC infrastructures, specifically focusing on Advanced Power Management, Debug/Trace Architectures, and bridging the gap between Pre-Silicon Verification and Post-Silicon Validation. You will collaborate closely with Architecture, RTL Design, Firmware, and Lab Validation teams to ensure high-quality silicon execution   THE PERSON:  You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  - Power Management Verification: Architect and execute power-aware verification strategies. Validate low-power states, power controller units (PMU), dynamic voltage and frequency scaling (DVFS), and clock/reset sequencing using UPF/CPF-based simulations. - Debug Architecture Validation: Own the verification of complex SoC debug and trace infrastructure, including JTAG, hardware triggers, breakpoints, and specialized trace networks (e.g., ARM CoreSight). - C-Based & UVM Environments: Develop, scale, and maintain advanced hybrid verification environments leveraging both SystemVerilog/UVM and C/C++ direct environments for system-level use-case verification. - Post-Silicon Alignment: Author test content portable to emulation and post-silicon platforms. Collaborate with lab teams to mirror post-silicon failures in pre-silicon environments for rapid root-cause analysis. - Coverage & Sign-off: Drive complete functional, code, assertion (SVA), and scenario-based coverage closure to meet stringent silicon tape-out criteria   PREFERRED EXPERIENCE:  - - Core Experience: 8–12 years of hands-on experience in ASIC/SoC design verification with successful tape-out histories. - Low Power Expertise: Strong understanding of static and dynamic low-power concepts, UPF/CPF specifications, and Gate-Level Power-Aware Simulations (PAGLS). - Debug Protocol Knowledge: Deep understanding of JTAG, IEEE 1149.x, trace architectures, and processor-specific debug infrastructure (e.g., ARM, RISC-V, or x86). - Methodologies: Proficient in SystemVerilog, UVM, SystemVerilog Assertions (SVA), and assembly or C/C++ embedded programming for SoC bring-up. - SoC Infrastructure: Familiarity with high-speed protocols and fabrics, including AMBA (AXI, AHB, APB, CHI), memory controllers, and interrupt controllers.   ACADEMIC CREDENTIALS:  - Bachelors or Masters degree in computer engineering/Electrical Engineering