AMD—Senior RTL Silicon Design & Validation Engineer

Job description

Description: ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Senior RTL Silicon Design & Validation Engineer   As a member of the AECG Product Validation and Solutions Team within AMD you will develop and enable the next generation of PCIe technologies to power datacenter, acceleration, AI and communications markets. High speed PCIe connectivity is critical for modern technology and infrastructure that helps improve our lives. THE ROLE: At AMD you will help create leading edge PCIe technologies used in a wide variety of applications. The focus of this role is to design, plan and execute RTL design for new and existing PCIe technology and solutions for programmable silicon at AMD. Key development includes PCIe technologies for PCIe Gen6/Gen7, CXL, TDISP, IDE, PCIe in-line DMA and other leading edge products. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. You should also have a desire to expand existing skill sets and take on new challenges.   KEY RESPONSIBILITIES: - Develop and productize next generation PCIe, CXL and connectivity solutions to power datacenter, acceleration, AI and communications markets - Participate in technical role in all phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for IPs - Develop comprehensive testing plans including Compliance and Interop testing. Critically review and provide feedback on the Design Implementations and Verification plans - Pre-Silicon and Post Silicon validation for new PCIe enabled blocks - Responsible for IP design, Silicon bring up, Validation and IP release - Work in collaboration with the Global teams PREFERRED EXPERIENCE: - Strong knowledge in RTL coding, preferably with Verilog and SystemVerilog - Proficient in RTL simulation tools (VCS, Modelsim) - Knowledge of high-speed interfaces including, PCIe, CXL, NVMe, Ethernet, DDR, LPDDR, HBM, AMBA AXI/AHB/APB protocol - Experience in using Lab equipment like PCIe Lecroy/Viavi Exerciser/Analyzer - Experience in developing system or IP prototypes using FPGAs - Strong knowledge of IP/SOC design methodologies - Experience with scripting languages including Tcl, Perl, Python, Unix shells and Makefiles - Knowledge of C/C++ is an added advantage   ACADEMIC CREDENTIALS:  - Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+Yrs of exp #LI-DB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. Responsibilities: Senior RTL Silicon Design & Validation Engineer   As a member of the AECG Product Validation and Solutions Team within AMD you will develop and enable the next generation of PCIe technologies to power datacenter, acceleration, AI and communications markets. High speed PCIe connectivity is critical for modern technology and infrastructure that helps improve our lives. THE ROLE: At AMD you will help create leading edge PCIe technologies used in a wide variety of applications. The focus of this role is to design, plan and execute RTL design for new and existing PCIe technology and solutions for programmable silicon at AMD. Key development includes PCIe technologies for PCIe Gen6/Gen7, CXL, TDISP, IDE, PCIe in-line DMA and other leading edge products. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. You should also have a desire to expand existing skill sets and take on new challenges.   KEY RESPONSIBILITIES: - Develop and productize next generation PCIe, CXL and connectivity solutions to power datacenter, acceleration, AI and communications markets - Participate in technical role in all phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for IPs - Develop comprehensive testing plans including Compliance and Interop testing. Critically review and provide feedback on the Design Implementations and Verification plans - Pre-Silicon and Post Silicon validation for new PCIe enabled blocks - Responsible for IP design, Silicon bring up, Validation and IP release - Work in collaboration with the Global teams PREFERRED EXPERIENCE: - Strong knowledge in RTL coding, preferably with Verilog and SystemVerilog - Proficient in RTL simulation tools (VCS, Modelsim) - Knowledge of high-speed interfaces including, PCIe, CXL, NVMe, Ethernet, DDR, LPDDR, HBM, AMBA AXI/AHB/APB protocol - Experience in using Lab equipment like PCIe Lecroy/Viavi Exerciser/Analyzer - Experience in developing system or IP prototypes using FPGAs - Strong knowledge of IP/SOC design methodologies - Experience with scripting languages including Tcl, Perl, Python, Unix shells and Makefiles - Knowledge of C/C++ is an added advantage   ACADEMIC CREDENTIALS:  - Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+Yrs of exp #LI-DB2