AMD—DFx-DV Engineer

Job description

Description: ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Sr SILICON DESIGN ENGINEER - DFT VERIFICATION THE ROLE: We are looking for an adaptive, self-motivated design for test verification engineer to join our growing server SOC DFT team. Identified candidate will be responsible for high quality verification of our DFT features for next generation server SOCs. This team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion design for test, and verification. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: - Create and execute test plans for DFT features for next generation EPYC server SOCs. - Carryout verification of DFT features such as JTAG/1500/1687, MBIST, Scan, Fuse, Clocks, Resets, high speed IO testing and much more at SOC level. - Will be creating test bench and verification infra using SV or C++. - Debug regression test failures and root cause design issues, identify verification gaps and address the same. - Debug fails and root cause them to design / verification issues. - Planning and projecting timelines for areas owned such as test plan creation, test writing, development of verification components, pattern generation etc. - Collaborate with large set of stakeholders such as architects, design engineers, functional verification engineers, post silicon engineers etc. - Work on code and functional coverage. - Generate patterns for post silicon testing and support ATE bring up. - Carryout post silicon debugs and help post silicon team achieve high coverage. - Work on emulation platforms to augment verification. PREFERRED EXPERIENCE: - Prior experience in verifying DFT features at subsystem / SOC level. - Proficient in standard simulation & debug tools such as VCS, Verdi etc. - Experienced with Verilog, C, C++, Linux and Windows environments. - Scripting language experience: Perl, Python,Ruby, Makefile, shell preferred.   - Knowledge in few of the DFT features such as JTAG, Memory BIST, Logic BIST, Scan, ATPG is highly desirable - Exposure to post silicon debugs and bring up highly is desired. ACADEMIC CREDENTIALS: - - Bachelors or Masters degree in Electronics/Electrical Engineering. #LI-AA1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. Responsibilities: Sr SILICON DESIGN ENGINEER - DFT VERIFICATION THE ROLE: We are looking for an adaptive, self-motivated design for test verification engineer to join our growing server SOC DFT team. Identified candidate will be responsible for high quality verification of our DFT features for next generation server SOCs. This team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion design for test, and verification. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: - Create and execute test plans for DFT features for next generation EPYC server SOCs. - Carryout verification of DFT features such as JTAG/1500/1687, MBIST, Scan, Fuse, Clocks, Resets, high speed IO testing and much more at SOC level. - Will be creating test bench and verification infra using SV or C++. - Debug regression test failures and root cause design issues, identify verification gaps and address the same. - Debug fails and root cause them to design / verification issues. - Planning and projecting timelines for areas owned such as test plan creation, test writing, development of verification components, pattern generation etc. - Collaborate with large set of stakeholders such as architects, design engineers, functional verification engineers, post silicon engineers etc. - Work on code and functional coverage. - Generate patterns for post silicon testing and support ATE bring up. - Carryout post silicon debugs and help post silicon team achieve high coverage. - Work on emulation platforms to augment verification. PREFERRED EXPERIENCE: - Prior experience in verifying DFT features at subsystem / SOC level. - Proficient in standard simulation & debug tools such as VCS, Verdi etc. - Experienced with Verilog, C, C++, Linux and Windows environments. - Scripting language experience: Perl, Python,Ruby, Makefile, shell preferred.   - Knowledge in few of the DFT features such as JTAG, Memory BIST, Logic BIST, Scan, ATPG is highly desirable - Exposure to post silicon debugs and bring up highly is desired. ACADEMIC CREDENTIALS: - - Bachelors or Masters degree in Electronics/Electrical Engineering. #LI-AA1