You will be taken to Cisco’s own careers page to apply. Job ID 2027050.
Job description
What You'll Do We are looking for a versatile and motivated Layout Engineer to join Cisco’s Silicon One Optics group an Engineering Team. In this role, you will support the physical implementation of high-performance analog and mixed-signal circuits for next-generation 100G, 200G, and 400G per lambda optical interconnect solutions. You will contribute to all phases of physical design—from concept through tapeout—primarily for block-level layouts while assisting with top-level integration. Working closely with circuit designers, packaging engineers, process teams, and product engineers, you will help develop robust, manufacturable layouts that meet performance, reliability, area, and schedule goals.
Specific responsibilities include
Support layout development and physical implementation of analog, mixed-signal circuits, high-speed interfaces (including SerDes and PAM4), and supporting digital blocks
Participate in block-level floor planning, placement, routing, and integration for sophisticated mixed-signal ICs
Collaborate with circuit designers to translate schematics and performance targets into optimized physical layouts
Optimize layouts for electrical performance, matching, parasitic, signal/power integrity, thermal behavior, yield, and manufacturability
Ensure compliance with all foundry design rules (DRC, LVS, ERC, density, EM/IR, and reliability requirements)
Assist in integration across analog, digital, and high-speed domains, including support for top-level assembly of SerDes, PAM4 paths, clocking, and control logic
Review post-layout extraction results and support simulation closure
Follow best practices for symmetry, shielding, isolation, and signal integrity
Partner with packaging and product teams on bump planning, pad ring, ESD structures, and package integration
Identify and help resolve layout-related issues impacting performance, yield, or production readiness
Participate in layout reviews and provide feedback on feasibility, tradeoffs, and tapeout risks
Collaborate with CAD teams to improve layout flows, automation, and efficiency
Support tapeout readiness, including database checks and signoff
Assist senior engineers with mentoring more junior layout team members and embrace strong layout methodology
Support silicon bring-up, debug, and failure analysis for layout-related issues
Who You’ll Work With As a Layout Engineer in the Client Optics Group (COG) Engineering Team, you will collaborate with a multidisciplinary team including analog/mixed-signal circuit designers, digital designers, verification engineers, package engineers, process technologists, CAD specialists, reliability experts, and post-silicon validation teams. You will partner with architects and designers during concept and planning phases, chip in to layout execution during design, work with signoff teams prior to tapeout, and support debug efforts post-silicon when layout-related issues arise. This role is a great opportunity to grow while helping deliver high-speed electrical IPs such as SerDes, PAM4 interfaces, D2D PHY, clocking subsystems, and control logic.
Who You Are
Bachelor’s degree in Electrical Engineering or related field (Master’s preferred)
4 to 5 years proven experience in custom IC layout for analog, mixed-signal, and high-speed designs
Solid technical skills with a curiosity about growing into layout leadership; strong foundation in matching, symmetry, shielding, parasitic control, thermal management, and signal integrity
Good knowledge of device-level layout techniques (common-centroid, interdigitation, guard rings, isolation structures)
Proficiency with industry-standard tools such as Cadence Virtuoso and Calibre (or equivalent)
Understanding of DRC, LVS, ERC, parasitic extraction, EM/IR analysis, and physical signoff flows
Familiarity with ASIC/SoC tapeout processes is helpful
Experience with scripting (Python, Perl, or TCL) for layout automation is a plus
Comfortable working in Linux environments
Excellent analytical, problem-solving, communication, and partnership skills
Demonstrated ability to chip in optimally and grow as a technical leader in a fast-paced environment
Ability to work as a team player with cross-functional teams spread across geo-locations.
Minimum Qualifications
Bachelor’s or Master’s or equivalent experience in Electrical Engineering or equivalent field
3+ years of layout design experience in analog, mixed-signal, or high-speed IC development
Hands-on experience supporting block-level layout efforts through tapeout
Strong skills in custom layout design, physical verification, and parasitic-aware implementation
Experience with Cadence or similar custom layout tools
Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.
Disclaimer To ensure that we hire the best talent in the right way, we follow a strict hiring process and recently, Cisco has been made aware of fraudulent recruiters claiming to be from the company. Please be advised that any communication from Cisco about careers will:
be in direct response to an application you have submitted through the company career site
begin with screening or an interview
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Required skills
layout review, lvs, bump planning, erc, linux, signal integrity, perl, mixed-signal circuit layout, em/ir analysis, python, block-level layout, high-speed ic design, calibre, thermal management, asic layout design, mentoring, cross-functional collaboration, tapeout process, analog circuit layout, tcl, pad ring design, esd structures, device-level layout techniques, parasitic extraction, package integration, drc
