ASIC Physical Design, Senior Staff Engineer

We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical design, taking complex IP from RTL to GDS, and you know that the difference between a design that tapes out on schedule and one that slips is usually a decision you made during floorplanning or a timing path you caught in week two instead of week ten. You have seen enough 5nm and below tapeouts to know where the landmines are buried, and you are the engineer who spots them before they blow up the schedule. You do not wait for perfect specs. When the RTL is still settling and the foundry deck has a known issue, you start floorplanning anyway because you know what matters and what can wait. You have strong opinions about ICC2 strategies, about when to push timing versus area, about which corners actually matter for signoff. You are comfortable defending those opinions in a room full of architects and verification leads, and you are equally comfortable changing your mind when the data says you should. At Synopsys, you will be working on UCIe PHYs and testchips that define how chips connect in the next generation of systems. The designs are real, the nodes are leading edge, and the team expects you to lead, not just execute. What You'll Be Doing