LEC/CLP Engineer

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MTS LEC and CLP SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan and execute the LEC and CLP of IP Subsystems and its signoff. This involves ownership of LEC and CLP at all physical partition level. KEY RESPONSIBILITIES:

• Responsible for LEC and CLP of all physical partitions of a device including its waivers, reviews and signoff
• Collaborate and support with design and/or implementation teams to achieve closure.
• Drive this activity with set of engineers by planning work and presenting regular status.
• Debug failure/issues and drive them to closure by working with CAD team or EDA vendor if required

PREFERRED EXPERIENCE:

• Highly Experienced in LEC and CLP with Synopsys or Cadence tool set.
• Complete Understanding of synthesis and Low power flows including UPF
• Have handled blocks with complex designs and their LEC/CLP lssues
• Have debug experience to solve issues.