You will be taken to AMD’s own careers page to apply. Job ID 93399.
Job description
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
IR/EM Lead Job Summary The IR/EM Lead will drive reliability signoff and closure for advanced SoC and IP designs, ensuring robust power delivery and electromigration compliance across all project phases. This role requires deep expertise in power integrity, IR drop analysis, electromigration verification, methodology development, and cross-functional technical leadership to enable successful tapeouts at advanced process technologies. Key Responsibilities
Lead all IR/EM activities for complex SoC and IP programs from floorplan through tapeout.
Define and drive project-wide IR/EM closure strategies, schedules, and signoff criteria.
Perform and review static and dynamic IR-drop analysis across full-chip and block-level designs.
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Lead electromigration analysis and closure for power grids, clock networks, signal routing, and package interfaces.
Collaborate closely with Physical Design, Package Design, Power Architecture, Clock, RTL, CAD, and Technology teams.
Identify power integrity risks early and drive mitigation plans through implementation and signoff stages.
Develop and deploy methodologies, automation, dashboards, and best practices to improve IR/EM convergence.
Guide teams in power grid architecture, decap planning, bump assignment, power distribution optimization, and reliability improvements.
Drive technical reviews and communicate design health, risks, and recommendations to project leadership.
Mentor engineers and provide technical leadership across multiple projects.
Technical Requirements
Strong expertise in Power Integrity and Electromigration analysis methodologies.
Deep understanding of:
Static and Dynamic IR Analysis
Electromigration Verification
Power Grid Design and Optimization
Decap Planning and Analysis
Voltage Drop Debug and Closure
Advanced Node Reliability Requirements
Hands-on experience with industry-standard IR/EM signoff tools.
Strong scripting and automation skills (Python, Tcl, Perl, or similar).
Strong understanding of advanced-node physical design implementation flows.
Leadership Expectations
Act as the primary technical owner for IR/EM signoff and closure.
Drive technical decisions impacting product reliability and design quality.
Influence implementation methodology across project and organizational boundaries.
Lead root-cause analysis for power integrity issues and drive systematic improvements.
Coach engineers and establish technical best practices for reliability signoff.
Qualifications
BS/MS in Electrical Engineering, Computer Engineering, or related discipline.
Typically 5-15 years of experience in Physical Design, Power Integrity, Reliability Analysis, or Signoff Engineering.
Proven experience leading IR/EM closure for large SoC designs through successful tapeout.
Preferred Qualifications
Experience with 5nm, 4nm, 3nm, or newer process technologies.
Understanding of package and system-level power delivery networks.
Familiarity with thermal analysis and reliability methodologies.
Experience developing automation and signoff productivity frameworks.
Strong communication and project leadership skills.
Success Metrics
First-pass IR/EM signoff readiness.
Timely closure of power integrity and reliability issues.
Improved methodology efficiency and signoff turnaround time.
Reduced late-stage design risk and tapeout escapes.
Effective mentorship and technical leadership across the organization.
#LI-BM2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Responsibilities
IR/EM Lead Job Summary The IR/EM Lead will drive reliability signoff and closure for advanced SoC and IP designs, ensuring robust power delivery and electromigration compliance across all project phases. This role requires deep expertise in power integrity, IR drop analysis, electromigration verification, methodology development, and cross-functional technical leadership to enable successful tapeouts at advanced process technologies. Key Responsibilities
Lead all IR/EM activities for complex SoC and IP programs from floorplan through tapeout.
Define and drive project-wide IR/EM closure strategies, schedules, and signoff criteria.
Perform and review static and dynamic IR-drop analysis across full-chip and block-level designs.
Lead electromigration analysis and closure for power grids, clock networks, signal routing, and package interfaces.
Collaborate closely with Physical Design, Package Design, Power Architecture, Clock, RTL, CAD, and Technology teams.
Identify power integrity risks early and drive mitigation plans through implementation and signoff stages.
Develop and deploy methodologies, automation, dashboards, and best practices to improve IR/EM convergence.
Guide teams in power grid architecture, decap planning, bump assignment, power distribution optimization, and reliability improvements.
Drive technical reviews and communicate design health, risks, and recommendations to project leadership.
Mentor engineers and provide technical leadership across multiple projects.
Technical Requirements
Strong expertise in Power Integrity and Electromigration analysis methodologies.
Deep understanding of:
Static and Dynamic IR Analysis
Electromigration Verification
Power Grid Design and Optimization
Decap Planning and Analysis
Voltage Drop Debug and Closure
Advanced Node Reliability Requirements
Hands-on experience with industry-standard IR/EM signoff tools.
Strong scripting and automation skills (Python, Tcl, Perl, or similar).
Strong understanding of advanced-node physical design implementation flows.
Leadership Expectations
Act as the primary technical owner for IR/EM signoff and closure.
Drive technical decisions impacting product reliability and design quality.
Influence implementation methodology across project and organizational boundaries.
Lead root-cause analysis for power integrity issues and drive systematic improvements.
Coach engineers and establish technical best practices for reliability signoff.
Qualifications
BS/MS in Electrical Engineering, Computer Engineering, or related discipline.
Typically 5-15 years of experience in Physical Design, Power Integrity, Reliability Analysis, or Signoff Engineering.
Proven experience leading IR/EM closure for large SoC designs through successful tapeout.
Preferred Qualifications
Experience with 5nm, 4nm, 3nm, or newer process technologies.
Understanding of package and system-level power delivery networks.
Familiarity with thermal analysis and reliability methodologies.
Experience developing automation and signoff productivity frameworks.
Strong communication and project leadership skills.
Success Metrics
First-pass IR/EM signoff readiness.
Timely closure of power integrity and reliability issues.
Improved methodology efficiency and signoff turnaround time.
Reduced late-stage design risk and tapeout escapes.
Effective mentorship and technical leadership across the organization.
#LI-BM2
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