Physical Design (PD) Lead

Physical Design (PD) Lead Location: Bangalore, India | Company: LTSCT — L&T Semiconductor Technologies Limited Reporting To: Chandra — Senior Architect, DC HW Systems | Experience: 10+ years (mandatory) Role Summary The Physical Design Lead owns the loop from architecture to silicon realization for the full xPU SiP. You will drive floorplanning, place-and-route, physical verification, timing closure, and signoff across ~800mm² chiplets on TSMC 2nm, acting as the primary bridge between the front-end architecture team and the backend PD organization. This is a hands-on leadership role accountable for delivering manufacturable, timing-clean, power-efficient physical databases for tapeout. Key Responsibilities

• Own full-chip and block-level floorplanning strategy for ~800mm² 2nm compute chiplets, including power grid planning, macro placement, and partitioning of dual BFOS arrays, SRAM banks, and NoC planes.
• Drive place-and-route, clock tree synthesis, and congestion/utilization optimization to meet 2 GHz operating frequency targets.
• Lead static timing analysis and timing closure across all corners, modes, and PVT conditions, resolving setup/hold, cross-talk, and signal-integrity violations.
• Own physical verification signoff — DRC, LVS, antenna, ERC, and DFM — and drive clean handoff to the foundry for tapeout.
• Manage power integrity (IR-drop, EM) and thermal-aware placement for high-density PE arrays operating at datacentre power envelopes.