Senior Staff Engineer - DFT

#WeAreIn to leverage synergies contributing to Infineon’s product development. Are you in?

Your role Key responsibilities in your new role

• Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip
• Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures
• Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification
• Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck at/TDF/Bridging/Cell-aware/iddq fault models
• Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations
• Hands on experience in analysis and debug of above-mentioned test domains
• Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out

Your profile Qualifications and skills to help you succeed

• Bachelor's degree (B.E./B.Tech.) in Electrical/Electronics Engineering or Master's degree (M.E./M.Tech.) in VLSI Design or a related field

• 12+ years of experience in DFT implementation, verification, and post-silicon debug

• Strong understanding of the complete ASIC design flow

• Hands-on experience with LEC, CLP, and power analysis methodologies is highly desirable

• Proven expertise in delivering complex SoC designs, encompassing DFT specification development, implementation, verification, and post-silicon debug