Sr. Memory Layout Design Engineer

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Job Description

Job Requirements:

• Minimum 8 years of experience with strong layout knowledge
• Bachelor's degree required.
• Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).
• Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).
• Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.

Job Description:

• Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.
• Manage scheduling, timelines, and layout floor-planning.
• Responsible for start to end deliverables with quality within the planned schedule.
• Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.
• Able to think and help in layout scripting and automation

Skill Set (Memory):

• Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.