Staff Engineer Verification -IP Digital Functional Verification

#WeAreIn to make sure that our circuits are designed to perfection. Are you in?

Your role Key responsibilities in your new role

• Lead

subtasks in IP/SoC verification. Contribute significantly to the verification of complex IPs/SoCs

• Create

verification requirements at the IP/SoC level based on design requirements and develop UVM test benches and formal verification environments

• Support

the development of verification infrastructure at the IP/chip level as required

• Support

different areas of IP verification, including RTL simulation, formal verification, power-aware verification, and gate-level simulation

Your profile Qualifications and skills to help you succeed

• Bachelor's degree (B.E./B.Tech.) in Electrical/Electronics Engineering or Master's degree (M.E./M.Tech.) in VLSI Design or a related field

• Minimum 5+years of relavent experince
• Strong understanding of ASIC verification methodologies, concepts, and industry best practices

• Proficient in Verilog, SystemVerilog,and UVM with hands-on experience in verification environment development

• Proven ability to develop and maintain IP and SoC-level testbenches for complex semiconductor designs