ASIC Digital Design - Staff Engineer

We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are You have spent years learning that the hardest bugs to catch are the ones simulation will never hit, and you have built the muscle to prove they cannot happen at all. Formal verification is not a side skill for you, it is the primary tool you reach for when correctness matters more than coverage metrics. You know that a well-written assertion is worth a thousand directed tests, and you have debugged enough counterexamples at 3 a.m. to tell the difference between a real bug, a missing assumption, and a property that was just worded wrong. Reading RTL is second nature. You can look at a state machine or a FIFO controller and start sketching the properties in your head before anyone asks. When a proof will not close, you do not give up, you add a cut point, split the case, tighten the constraint, or abstract the helper logic until the engines can finish. You have worked with designers who trust formal and designers who do not yet, and you have learned how to bring both groups along. At Synopsys, you will own formal sign-off for real blocks that ship in customer silicon, and you will help build the next generation of verification engineers who think proof-first.