Synthesis STA silicon design Engineer

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MTS Synthesis STA silicon design Engineer THE ROLE: The focus of this role is to lead by planning and executing the front end implementation of IP Subsystem and its physical partitions. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on tenchical issues.

KEY RESPONSIBILITIES

• Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure
• Collaborate with designer and PNR teams to achieve closure.
• Understand duration required, plan and execute as per schedule.
• Complete quality delivery for synthesis and timing closure.
• Debug and resolve technical issues

PREFERRED EXPERIENCE:

• Highly experienced in synthesis, LEC, CLP and timing closure
• Experience in place and route (PNR) is plus.