Timing Constraint Development Engineer

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MTS Timing constraint development ENGINEER

THE ROLE: The focus of this role is to plan and develop the Timing constraints of IPs Subsystem or Full chip. This involves ownership of SDC development, SDC generation, verification, promotion/demotion and equivalence checking. The role might also epxand to (if needed) synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on technical issues.

KEY RESPONSIBILITIES

• Main responsibility is to own constratins, SDC developement for IPs, SS and SoCs. Including SDC generation, verification, promotion, demotion and equivalence using third party or self built tools.
• Prior experience with Lint, CDC and RTL & Netlist based static checks is a plus
• Collaborate with designer and PNR teams to achieve closure.
• Understand duration required, plan and execute as per schedule.