PNR CAD SILICON DESIGN ENGINEER

Location Hyderabad, India
Experience 8-10 yrs
Job type Full-time
Posted 5 Oct 2026
Qualification Master's / Bachelor's (Engineering)

Apply on Official Website

You will be taken to AMD’s own careers page to apply. Job ID 93169.

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

PNR CAD SILICON DESIGN ENGINEER THE ROLE: This position for a CAD Engineer will be critical to shaping the next generation AMD products, the leader in GPU, CPU. It requires interfacing with large design teams across the globe and owning development & support for next generation synthesis, place and route flows. Successful candidate would be responsible for automation of PnR flows and methodologies for the 3nm & 2nm technology nodes as well as working closely with the EDA vendors to identify innovative solutions and track methodology issues.

THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems KEY RESPONSIBILITIES:

Responsible for developing Place and Route methodologies for various designs at advanced technology nodes

Responsibilities

Responsible for developing Place and Route methodologies for various designs at advanced technology nodes
Work seamlessly with synthesis and signoff (STA, extraction, Physical Verification) teams to achieve best-in-class PPA
Drive power/performance/area (PPA) convergence for SOCs implementation
Script out utilities to automate different stages of the implementation flow
Support design teams at global sites through multiple PnR flow stages including chip finish flows
CAD flow and Methodology development on advanced process nodes such as 3nm, 2nm are preferred

PREFERRED EXPERIENCE:

Hands‑on experience in PNR flows including multi-voltage & power-gated designs
Expertise with industry‑standard physical design tools Innovus & Fusion Compiler
Experience with synthesis, STA, Physical verification domains is a plus
Strong understanding of low-power flows includes UPF concepts, power-gating, isolation, level-shifter, voltage areas, power-state tables, electrical checks using FM & VSI
Proficiency in scripting and automation using Python, TCL with strong debugging capabilities and CAD‑automation mindset.
Exposure to AI/ML concepts, with strong Python proficiency.
CAD and Automation mindset

ACADEMIC CREDENTIALS

Master’s/Bachelor’s Degree in Electronics Engineering (Minor in Computer Science preferred)
8-10 years of experience in CAD flow and methodology development on advanced nodes such as 3nm & 2nm
Work closely with design teams to support multiple areas through Netlist to GDSII implementation
Strong problem-solving skills and analytical thinking
Team player, good work ethic, and excellent communication skills
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